Thermo-mechanical analysis of advanced electronic packages in early system design

被引:6
|
作者
Sommer, JP [1 ]
Wittler, O
Manessis, D
Michel, B
机构
[1] Fraunhofer Inst Reliabil & Micro Integrat IZM, Dept Mech Reliabil & Micro Mat, Berlin, Germany
[2] Tech Univ Berlin, Micro Peripher Technol Ctr, D-13355 Berlin, Germany
来源
MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS | 2005年 / 12卷 / 1-2期
关键词
Solder Bump; Power Transistor; Wafer Level; Parametric Finite Element Analysis; Wafer Level Package;
D O I
10.1007/s00542-005-0024-8
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The thermal and thermo-mechanical behaviour of advanced electronic packages should be taken into account from the initial design phase in order to achieve a high level of reliability. Numerical studies by means of finite element (FE) analyses are very useful in order to reveal and evaluate the essential thermal and mechanical influences which are induced during manufacturing, storing, transport, and operation. Two different types of packages are under investigation, an RF-system on chip including digital and analogue parts on one chip (RF SoC), and combined in a BGA-type package, made by Shellcase Ltd, and a power transistor with all contacts on one side. Parametric FE analyses are presented in order to pre-optimise the shape of the interconnects and to improve the compliance between stiff components before prototyping and real testing.
引用
收藏
页码:75 / 81
页数:7
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