A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier

被引：4

作者：

Peng, Chunyu ^{[1
]}

Tao, Youwu ^{[1
]}

Lu, Wenjuan ^{[1
]}

Li, Zhengping ^{[1
]}

Ji, Xinchun ^{[2
]}

Yan, Jinlong ^{[1
]}

Chen, Junning ^{[1
]}

机构：

[1] Anhui Univ, Sch Elect & Informat Engn, Hefei 230601, Peoples R China

[2] Nanjing Univ Posts & Telecommun, Coll Elect Sci & Engn, Nanjing 210001, Jiangsu, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2015年 / 12卷 / 05期

基金：

中国国家自然科学基金;

关键词：

replica bitline; sense amplifier enable; timing process-variation; cycle time;

D O I：

10.1587/elex.12.20150102

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel cascade control replica bitline delay (CCRBD) technique has been proposed to reduce timing process-variation of SRAM sense amplifier in this brief. The main idea of this technique is that both replica bitlines (RBLs) are utilized, and one is cascade controlled by the other. Simulation results show that the timing process-variation of this technique decreases by 41.83% compared with conventional strategy. Simultaneously, the cycle time is also reduced by 19% at the supply voltage of 800 mV in TSMC 65 nm technology. Additionally, the area of the proposed scheme is nearly the same as that with conventional replica bitline technique.

引用

页数：8

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