Design and implementation of a micro-power CMOS voltage reference circuit based on thermal compensation of Vgs

被引:8
作者
Chouhan, Shailesh Singh [1 ]
Halonen, Kari [1 ]
机构
[1] Aalto Univ, Dept Micro & Nano Sci, Espoo, Finland
关键词
MOS voltage reference; Line regulation; Vgs thermal compensation; Power-supply rejection ratio; Temperature coefficient; PPM/DEGREES-C; DIFFERENCE;
D O I
10.1016/j.mejo.2014.09.015
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work a simple all MOS voltage reference circuit has been proposed. To obtain reference output voltage, the thermal compensation has been generated by using a series composite NMOSTs. The voltage reference circuit has been fabricated in a standard 0.18 mu m CMOS technology. The proposed circuit is capable of working for the supply voltage ranging from 1.25 V to 2 V. The maximum power dissipation of the proposed circuit is 0.48 mu W at the supply voltage of 2 V. The measurement has been performed over a set of 10 samples. It resulted in the mean temperature coefficient (TC) of 19.302 ppm/degrees C for the temperature range of -40 degrees C to 85 degrees C. The measured mean line sensitivity is 2217 mV/V for the supply voltage ranging from 125 V to 2 Vat the room temperature. The measured mean power supply rejection ratio at 10 Hz and 1 MHz is -55.31 dB and -16.67 dB respectively for the supply voltage of 1.8 V. Moreover, the measured mean noise density without any filtering capacitor at 100 Hz and 100 kHz are 12.39 mu V/root Hz and 0.39 mu V/root Hz respectively. Due to its simple circuit implementation, the active area of the circuit is 0.0077 mm(2). (C) 2014 Elsevier Ltd. All rights reserved.
引用
收藏
页码:36 / 42
页数:7
相关论文
共 28 条
[1]  
Abu-Rahma Mohamed Hassan, 2008, THESIS U WATERLOO
[2]  
Arora N., 2006, MOSFET Modeling for VLSI Simulation
[3]   Untrimmed 6.2 ppm/°C bulk-isolated curvature-corrected bandgap voltage reference [J].
Basyurt, Pinar Basak ;
Aksin, Devrim Yilmaz .
INTEGRATION-THE VLSI JOURNAL, 2014, 47 (01) :30-37
[4]  
Brokaw P., 2013, IEEE SOLID STATE CIR, V5, P37
[5]   Threshold-voltage-difference-based CMOS voltage reference derived from basic current bias generator with 4.3 ppm/°C temperature coefficient [J].
Cai Yongda ;
Zou Zhige ;
Wang Zhen ;
Lei Jianming .
ELECTRONICS LETTERS, 2014, 50 (07) :505-506
[6]   A sub 1 V high PSRR CMOS bandgap voltage reference [J].
Chahardori, Mohammad ;
Atarodi, Mojtaba ;
Sharifkhani, Mohammad .
MICROELECTRONICS JOURNAL, 2011, 42 (09) :1057-1065
[7]   Ultra-low-power temperature compensated voltage reference generator [J].
De Vita, Giuseppe ;
Iannaccone, Giuseppe .
MICROELECTRONICS JOURNAL, 2006, 37 (10) :1072-1079
[8]   A reliable demodulator and a power regulation circuit with an accurate and small-size voltage reference in UHF RFID [J].
Du, Yongqian ;
Zhuang, Yiqi ;
Li, Xiaoming ;
Liu, Weifeng ;
Qi, Zengwei ;
Yin, Yue .
MICROELECTRONICS JOURNAL, 2013, 44 (02) :72-79
[9]  
Filanovsky I. M., 2005, 2005 48th IEEE International Midwest Symposium on Circuits and Systems (IEEE Cat. No. 05CH37691), P1790
[10]   Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits [J].
Filanovsky, IM ;
Allam, A .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 2001, 48 (07) :876-884