3D NAND vertical channel defect inspection and classification solution on a DL-based e-beam system

被引:1
|
作者
Wu, Cheng Hung [1 ]
Sun, Yen Chun Chuan [2 ]
Kushwaha, Rishabh [3 ]
Bajpai, Piyush [4 ]
Cheng, Shao Chang [2 ]
机构
[1] KLA, GPG CE TWN Inspect, Tainan, Taiwan
[2] KLA, GPG CE TWN Inspect, Hsinchu, Taiwan
[3] KLA, GPG EBEAM Apps, Milpitas, CA USA
[4] KLA, GPG EBEAM Apps, Chennai, Tamil Nadu, India
关键词
3D NAND; high aspect ratio (HAR); high landing energy (HiLE); defect inspection; deep learning (DL);
D O I
10.1109/ASMC54647.2022.9792511
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
With data storage capacity increasing, more memory cell stacks for three-dimensional NAND (3D NAND) devices are developed. When stacking more thin-film layers, the capability to form uniform high aspect ratio (HAR) structures becomes a key 3D NAND process step. Therefore, in 3D NAND manufacturing, etch process control is especially important. Etch processes generate HAR structures and defects are usually buried in the deep trenches or holes, which become inspection challenges. Defect control is important for semiconductor manufacturing to ensure device quality. In this study, a high landing energy (HiLE) e-beam defect inspection system with a wide landing energy operation range is utilized to compare scanning electron microscopy (SEM) images of different landing energy to get the best signal for defects of interest (DOI) that are buried in the deep vertical channel (VC) holes. A landing energy of 30KeV was determined to provide best DOI imaging. In addition, to reduce the burden of manual defect classification (MDC) and improve traditional algorithm limitations, a deep learning (DL)-based algorithm methodology is implemented that successfully demonstrates detection of DOI at similar to 6 mu m depth within the VC holes of a 96-layer 3D NAND device, while also achieving auto defect classification (ADC) with > 90% purity by each VC row.
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页数:4
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