A Lost Cycles Analysis for Performance Prediction using High-Level Synthesis

被引:1
作者
da Silva, Bruno [1 ]
Lemeire, Jan
Braeken, An
Touhafi, Abdellah
机构
[1] VUB, INDI, Brussels, Belgium
来源
APPLIED RECONFIGURABLE COMPUTING, ARC 2016 | 2016年
关键词
High-Level Synthesis; Lost cycles; FPGA; Performance prediction; Overhead analysis;
D O I
10.1007/978-3-319-30481-6_28
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Today's High-Level Synthesis (HLS) tools significantly reduce the development time and offer a fast design-space exploration of compute intensive applications. The difficulty, however, to properly select the HLS optimizations leading to a high-performance design implementation drastically increases with the complexity of the application. In this paper we propose as extension for HLS tools a performance prediction for compute intensive applications consisting of multiple loops. We affirm that accurate performance predictions can be obtained by identifying and estimating all overheads instead of directly modelling the overall execution time. Such performance prediction is based on a cycle analysis and modelling of the overheads using the current HLS tools' features. As proof of concept, our analysis uses Vivado HLS to predict the performance of a single-floating point matrix multiplication. The accuracy of the results demonstrates the potential of such kind of analysis.
引用
收藏
页码:334 / 342
页数:9
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