A Fine-Resolution Time-to-Digital Converter for a 5GS/s ADC

被引：0
|
作者：
Townsend, Kenneth A. [1 ]
Macpherson, Andrew R. [1 ]
Haslett, James W. [1 ]
机构：
[1] Univ Calgary, Schulich Sch Engn, TRLabs, Calgary, AB, Canada
来源：
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS | 2010年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents the architecture of a high-speed time-based Analog-to-Digital Converter (ADC) based on voltage-to-time and time-to-digital conversion. A tunable Time-to-Digital Converter (TDC) that is robust against process variation and suitable for embedding within a 3-bit ADC is discussed and its performance evaluated. Simulation shows that when the TDC is designed in a 90nm CMOS process it is capable of a DNL and INL less than +/-0.040LSB and +/-0.015LSB, respectively, for 9mW of power consumption at 5GS/s with a 6.25ps resolution.
引用
收藏
页码：3024 / 3027
页数：4
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