Framework of a Scalable Delay-Insensitive Asynchronous Platform Enabling Heterogeneous Concurrency

被引：0

作者：

Men, Liang ^{[1
]}

Di, Jia ^{[1
]}

机构：

[1] Univ Arkansas, Dept Comp Sci & Comp Engn, Fayetteville, AR 72701 USA

来源：

2014 IEEE 57TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2014年

关键词：

asynchronous circuit; heterogeneous platform; asynchronous arbiter; cascaded structure;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Parallel architecture of asynchronous circuits has great potential in improving throughput while reducing energy consumption. This paper presents a parallel platform designed using delay-insensitive asynchronous logic. Heterogeneous data processing units as well as datapath control logic are integrated in the platform. All these units share the common data I/O and external handshaking control channels. Asynchronous arbiters are incorporated to make the cores' data requests mutually exclusive. The highly-modular interface and delay-insensitivity allow the platform to be easily cascaded to construct large systems. Simulation results indicate the functional correctness of the heterogeneous platform as well as its cascaded structure.

引用

页码：113 / 116

页数：4

共 11 条

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