High-Speed Three-Phase Enhanced Phase-Locked Loop for Grid Synchronization Under Adverse Conditions

被引:0
作者
Gulipalli, Surya Chandra [1 ]
Gude, Srinivas [2 ]
Chu, Chia-Chi [1 ]
机构
[1] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu, Taiwan
[2] Delta Elect Inc, Adv Prod & Technol, Taoyuan, Taiwan
来源
2022 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE) | 2022年
关键词
Enhanced Phase-locked loop (EPLL); delayed signal cancellation (DSC); phase-locked loop (PLL); Multiple delayed signal cancellation (MDSC); grid frequency; harmonics; phase-angle; SYSTEM; DESIGN;
D O I
10.1109/ECCE50734.2022.9948044
中图分类号
TE [石油、天然气工业]; TK [能源与动力工程];
学科分类号
0807 ; 0820 ;
摘要
In this paper, a modified enhanced phase-locked loop (EPLL) is proposed for grid synchronization. This model can achieve a high speed estimation of voltage magnitude, phase, and frequency parameters of the grid voltage. This proposed model is based on the phase error compensation technique that results in immediate tracking of phase variations of the threephase grid voltage. The resultant input-output relationship of the phase angle is a simple transfer function with almost unity magnitude. One additional voltage loop is also included which can further assist in decoupling the voltage estimation variations due to phase or frequency changes. To enhance its dynamical performance even under adverse grid conditions with harmonics, an efficient Multiple Delayed Signal Cancellation (MDSC) prefilter is utilized. Real-time simulation results endorse that in case of polluted grid environment, a pre-filter is highly necessary and such a design overall transfer function is equivalent to the prefilter's transfer function.
引用
收藏
页数:7
相关论文
共 19 条
[1]  
[Anonymous], 2008, 50160 EN
[2]   A phase tracking system for three phase utility interface inverters [J].
Chung, SK .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2000, 15 (03) :431-438
[3]   More-Stable EPLL [J].
Golestan, Saeed ;
Matas, Jose ;
Abusorrah, Abdullah M. ;
Guerrero, Josep M. .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2022, 37 (01) :1003-1011
[4]   An Efficient Implementation of Generalized Delayed Signal Cancellation PLL [J].
Golestan, Saeed ;
Freijedo, Francisco D. ;
Vidal, Ana ;
Yepes, Alejandro G. ;
Guerrero, Josep M. ;
Doval-Gandoy, Jesus .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2016, 31 (02) :1085-1094
[5]   dq-Frame Cascaded Delayed Signal Cancellation-Based PLL: Analysis, Design, and Comparison With Moving Average Filter-Based PLL [J].
Golestan, Saeed ;
Ramezani, Malek ;
Guerrero, Josep M. ;
Monfared, Mohammad .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2015, 30 (03) :1618-1632
[6]  
Gude S, 2017, IEEE POW ENER SOC GE
[7]   Dynamic Performance Improvement of Multiple Delayed Signal Cancelation Filters Based Three-Phase Enhanced-PLL [J].
Gude, Srinivas ;
Chu, Chia-Chi .
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 2018, 54 (05) :5293-5305
[8]  
K-Ghartemani M., 2014, ENHANCED PHASE LOCKE
[9]   A novel three-phase magnitude-phase-locked loop system [J].
Karimi-Ghartemani, M. .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2006, 53 (08) :1792-1802
[10]   Robust and frequency-adaptive measurement of peak value [J].
Karimi-Ghartemani, M ;
Iravani, AR .
IEEE TRANSACTIONS ON POWER DELIVERY, 2004, 19 (02) :481-489