A 21-GS/s Single-Bit Second-Order Delta-Sigma Modulator for FPGAs

被引：32

作者：

Li, Haolin ^{[1
]}

Breyne, Laurens ^{[1
]}

Van Kerrebrouck, Joris ^{[1
]}

Verplaetse, Michiel ^{[1
]}

Wu, Chia-Yi ^{[1
]}

Demeester, Piet ^{[1
]}

Torfs, Guy ^{[1
]}

机构：

[1] Univ Ghent, Dept Informat Technol, IDLab, IMEC, B-9052 Ghent, Belgium

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2019年 / 66卷 / 03期

关键词：

Delta-sigma modulator; multi-stage noise shaping (MASH); software defined radio; quantization noise; FPGA; RADIO; DAC;

D O I：

10.1109/TCSII.2018.2855962

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new high-speed delta-sigma modulator (DSM) topology is proposed by cascading a bit reduction process with a multi-stage noise shaping MASH-1-1 DSM. This process converts the two-bit output sequence of the MASH-1-1 DSM to a single-bit sequence, merely compromising the DSM noise-shaping performance. Furthermore, the high clock frequency requirements are significantly relaxed by using parallel processing. This DSM topology facilitates the designs of wideband software defined radio transmitters and delta-sigma radio-over-fiber transmitters. Experimental results of the FPGA implementation show that the proposed low-pass DSM can operate at 21 GS/s, providing 520-MHz baseband bandwidth with 42.76-dB signal-to-noise-and-distortion ratio (SNDR) or 1.1-GHz bandwidth with 32.04-dB SNDR (based on continuous wave measurements). An all-digital transmitter based on this topology can generate 218.75MBd 256 QAM over 200-m OM4 multimode fiber in real time, with 7-GS/s sampling rate and an error vector magnitude below 1.89%.

引用

页码：482 / 486

页数：5

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