New Interconnect Evaluation Metric for High-Speed IO

被引：0

作者：

Moon, Se-Jung ^{[1
]}

Acar, Erkan ^{[1
]}

Mellitz, Richard ^{[2
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

[2] Intel Corp, Columbia, SC 95051 USA

来源：

2011 IEEE 20TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS) | 2011年

关键词：

design optimization; interconnect; spring-probe socket; high-speed IO; differential bus; RSM;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper proposes new frequency-domain (FD) metrics to evaluate and optimize interconnects for high-speed IO. In this paper, we focused on a spring-probe socket for interconnects and PCIe Gen3 for the high-speed IO. For design optimization, we adapted a holistic approach utilizing response surface methodology. Using the proposed metrics, the spring-probe socket design was optimized to minimize impact on the IO channel performance. In order to check the validity of the new metrics, an optimized socket design via voltage margin and timing margin from eye opening was compared.

引用

页码：81 / 84

页数：4

共 50 条

[21] Jittery Signal Generation for High-Speed Interconnect Simulation
Hollis, Timothy M.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2008, 55 (10) : 1046 - 1050
[22] REAL INDUCTANCE CALCULATION FOR HIGH-SPEED INTERCONNECT SYSTEMS
CANGELLARIS, AC
PRINCE, JL
PALUSINSKI, OA
PROCEEDINGS OF THE TECHNICAL CONFERENCE : EIGHTH ANNUAL INTERNATIONAL ELECTRONICS PACKAGING CONFERENCE, 1988, : 596 - 600
[23] Equalization Techniques for High-speed Serial Interconnect Transceivers
Wang, Hui
Cheng, Yuhua
2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 1581 - 1584
[24] Client/server way to interconnect high-speed LANs
ENSEEIT/IRIT Lab, Toulouse, France
Comput Commun, 8 (649-661):
[25] Interconnect energy dissipation in high-speed ULSI circuits
Heydari, P
Pedram, M
ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2002, : 132 - 137
[26] Coupled High-Speed Interconnect Analysis on Parallel Platforms
Paul, D.
Nakhla, N. M.
Achar, R.
Nakhla, M. S.
IEEE EDAPS: 2008 ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM, 2008, : 202 - 205
[27] High-speed Serial Interconnect Transceiver: Applications and Design
Wang, Hui
Cheng, Yuhua
2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4, 2008, : 1566 - 1571
[28] INTERCONNECT SYNTHESIS TOOL TARGETS HIGH-SPEED SYSTEMS
DONLIN, M
COMPUTER DESIGN, 1994, 33 (07): : 113 - 113
[29] ELECTRICAL PERFORMANCE OF HIGH-SPEED INTERCONNECT SYSTEMS.
Scheinfein, Michael R.
Liao, J.C.
Palusinski, Olgierd A.
Prince, John L.
1600, (CHMT-10):
[30] Fan Cooling Investigation for High-Speed Electronic Interconnect
Zhang, Taolue
Li, Qibo
Shankaran, Gokul
Amleshi, Peerouz
HEAT TRANSFER ENGINEERING, 2023, 44 (09) : 767 - 784

← 1 2 3 4 5 →