A 12-bit 20-MS/s pipelined ADC with nested digital background calibration

被引：17

作者：

Wang, X ^{[1
]}

Hurst, PJ ^{[1
]}

Lewis, SH ^{[1
]}

机构：

[1] Univ Calif Davis, Dept Elect & Comp Engn, Solid State Circuits Res Lab, Davis, CA 95616 USA

来源：

PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/CICC.2003.1249429

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 12-b 20-MS/s pipelined ADC is calibrated using an algorithmic ADC, which is itself calibrated. With background calibration, the peak SNDR and SFDR of the pipeline are 70.8 dB and 93.3 dB, respectively. The total power dissipation is 254 mW from 3.3 V The active area is 7.5 mm(2) in 0.35mum CMOS.

引用

页码：409 / 412

页数：4

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