A Machine Learning Approach to Predict Timing Delays During FPGA Placement

被引：8

作者：

Martin, T. ^{[1
]}

Grewal, G. ^{[1
]}

Areibi, S. ^{[2
]}

机构：

[1] Univ Guelph, Sch Comp Sci, Guelph, ON N1G 2W1, Canada

[2] Univ Guelph, Sch Engn, Guelph, ON N1G 2W1, Canada

来源：

2021 IEEE INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW) | 2021年

关键词：

Machine Learning; Timing Estimation; FPGA Placement;

D O I：

10.1109/IPDPSW52791.2021.00026

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Timing-driven placement tools for FPGAs rely on the availability of accurate delay estimates for nets in order to identify and optimize critical paths. In this paper, we propose a machine-learning framework for predicting net delay to reduce miscorrelation between placement and detailed-routing. Features relevant to timing delay are engineered based on characteristics of nets, available routing resources, and the behavior of the detailed router. Our results show an accuracy above 94%, and when integrated within an FPGA analytical placer Critical Path Delay (CPD) is improved by 10% on average compared to a static delay model.

引用

页码：124 / 127

页数：4

共 13 条

[1] Goodfellow I, 2016, ADAPT COMPUT MACH LE, P1
[2] Grewal G., GUELPH FPGA CAD GROU
[3] Kahng A., 2013, Proc. of DAC, P1
[4] Machine-Learning Based Congestion Estimation for Modern FPGAs
Maarouf, D.
Alhyari, A.
Abuowaimer, Z.
Martin, T.
Gunter, A.
Grewal, G.
Areibi, S.
Vannelli, A.
[J]. 2018 28TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), 2018, : 427 - 434
[5] Predicting interconnect delay for physical synthesis in a FPGA CAD flow
Manohararajah, Valavan
Chiu, Gordon R.
Singh, Deshanand P.
Brown, Stephen D.
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2007, 15 (08) : 895 - 903
[6] Martin T., 2019, DESIGN AUTOMATION C, P1
[7] Pedregosa F., 2011, J MACH LEARN RES, V12, P2825
[8] Qiu J., 2010, P 12 ACM IEEE INT WO, P77
[9] Wang GX, 2015, INT CONF MACH LEARN, P1, DOI 10.1109/ICMLC.2015.7340888
[10] Xilinx, 2016, ISPD 2016 Routability-Driven FPGA Placement Contest.

← 1 2 →