Dual-edge triggered static pulsed flip-flops

Two Simple structures of low-power Dual-edge triggered Static Pulsed Flip-Flops (DSPFF) are presented in this paper. They are composed of a dual-edge pulse generator and a static flip-flop with equal toggling delays. The static feature of DSPFF avoids unnecessary internal node transitions to reduce power consumption. Simple structure of pulse generator with double-edge triggering is proposed that results in low power dissipation in clock distribution networks. Power consumption of the DSPFF is observed to be the lowest among all high-performance flip-flops and latches. HSPICE simulation results at a frequency of 400 MHz show that the proposed DSPFF exhibits more than 24% PDP reduction compared to the hybrid-latch flip-flop (HLFF) and more than 14% PDP reduction compared to conditional-capture flip-flop (CCFF). The proposed DSPFF shows 64% power reduction in comparison to the HLFF and 59% power reduction in comparison to CCFF in practical circuits.