Minimal C-testable tests for block-CLA adders

被引：4
作者：
Moore, WR [1 ]
机构：
[1] Univ Oxford, Dept Engn Sci, Oxford OX1 3PJ, England
来源：
INTERNATIONAL JOURNAL OF ELECTRONICS | 1998年 / 85卷 / 05期
关键词：
D O I：
10.1080/002072198133897
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper examines the testing of Carry Look-Ahead (CLA) adders and block-CLA adders with inter-block carry-ripple. By analysing the testing and fault-effect propagation of each stage of the adder, the paper derives minimal test sets for simple CLAs. The generality of these allows them to be assembled to produce minimal 'C-testable' test sets for block-CLA adders. The special cases of unequal block sizes and of no carry-in are also covered. The paper also examines the differing test requirements of the two different forms of CLA adders, the exclusive-OR form and the inclusive-OR form.
引用
收藏
页码：611 / 628
页数：18
相关论文
共 12 条
  • [1] BATEK MJ, 1994, VLSI DESIGN, V1, P285
  • [2] ON THE GENERATION OF AREA-TIME OPTIMAL TESTABLE ADDERS
    BECKER, B
    DRECHSLER, R
    MOLITOR, P
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1995, 14 (09) : 1049 - 1066
  • [3] BHATTACHARYA D, 1990, HIERARCHICAL MODELIN
  • [4] EASILY TESTABLE ITERATIVE SYSTEMS
    FRIEDMAN, AD
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1973, C 22 (12) : 1061 - 1064
  • [5] *GEN CORP, 1995, SIMIC
  • [6] C-testable modified-booth multipliers
    Gizopoulos, D
    Nikolos, D
    Paschalis, A
    Halatsis, C
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1996, 8 (03): : 241 - 260
  • [7] Fast C-testable array multipliers
    Gizopoulos, D
    Nikolos, D
    Paschalis, A
    [J]. INTERNATIONAL JOURNAL OF ELECTRONICS, 1996, 80 (04) : 561 - 582
  • [8] TESTING VLSI REGULAR ARRAYS
    MARNANE, WP
    MOORE, WR
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1995, 6 (02): : 153 - 177
  • [9] MARNANE WP, 1989, EUR TEST C PAR, P304
  • [10] MOORE WR, 1997, 213297 OUEL
12