An orthogonal 6F2 trench-sidewall vertical device cell for 4Gb/16Gb DRAM

被引：9

作者：

Radens, CJ ^{[1
]}

Kudelka, S ^{[1
]}

Nesbit, L ^{[1
]}

Malik, R ^{[1
]}

Dyer, T ^{[1
]}

Dubuc, C ^{[1
]}

Joseph, T ^{[1
]}

Seitz, M ^{[1
]}

Clevenger, L ^{[1
]}

Arnold, N ^{[1
]}

Mandelman, J ^{[1
]}

Divakaruni, R ^{[1
]}

Casarotto, D ^{[1
]}

Lea, D ^{[1
]}

Jaiprakash, VC ^{[1
]}

Sim, J ^{[1
]}

Faltermeier, J ^{[1
]}

Low, K ^{[1
]}

Strane, J ^{[1
]}

Halle, S ^{[1
]}

Ye, Q ^{[1
]}

Bukofsky, S ^{[1
]}

Gruening, U ^{[1
]}

Schloesser, T ^{[1
]}

Bronner, G ^{[1
]}

机构：

[1] IBM Microelect, Semicond R&D Ctr, IBM Infineon DRAM Dev Alliance, Hopewell Junction, NY 12533 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904327

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a novel 6F(2) trench-capacitor DRAM with a trench-sidewall vertical-channel array transistor. The cell features a line/space pattern for the active area, single-sided buried-strap node contact, vertical transistor channel formed along the upper region of the trench capacitor, a device active area bounded by the isolation trench and capacitor collar, and a single bit contact per cell.

引用

页码：349 / 352

页数：4

共 8 条

[1]

Gruening U., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P25, DOI 10.1109/IEDM.1999.823838

[2] A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's [J].

Hoenigschmid, H ;

Frey, A ;

DeBrosse, JK ;

Kirihata, T ;

Mueller, G ;

Storaska, DW ;

Daniel, G ;

Frankowsky, G ;

Guay, KP ;

Hanson, DR ;

Hsu, LLC ;

Ji, B ;

Netis, DG ;

Panaroni, S ;

Radens, C ;

Reith, AM ;

Terletzki, H ;

Weinfurtner, O ;

Alsmeier, J ;

Weber, W ;

Wordeman, MR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (05) :713-718

[3]

LI Y, 1959, INT S VLSI TECH SYS, P251

[4]

Nesbit L., 1993, International Electron Devices Meeting 1993. Technical Digest (Cat. No.93CH3361-3), P627, DOI 10.1109/IEDM.1993.347282

[5]

RADENS C, 2000, S VLSI TECH

[6]

Richardson W. F., 1985, International Electron Devices Meeting. Technical Digest (Cat. No. 85CH2252-5), P714

[7]

RICHARDSON WF, 1989, S VLSI TECH, P65

[8]

Rupp T., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P33, DOI 10.1109/IEDM.1999.823840

← 1 →