New Hardware Architecture for Self-Organizing Map Used for Color Vector Quantization

被引:4
作者
Ben Khalifa, Khaled [1 ,2 ]
Blaiech, Ahmed Ghazi [1 ,2 ]
Abadi, Mehdi [1 ]
Bedoui, Mohamed Hedi [2 ]
机构
[1] Univ Sousse, Inst Super Sci Appliquees & Technol Sousse, Sousse 4003, Tunisia
[2] Univ Monastir, Fac Med Monastir, Lab Rech Technol & Imagerie Med, LR12ES06, Monastir 5019, Tunisia
关键词
Self-Organizing Map (SOM); Diagonal-SOM (D-SOM); Hardware implementation; FPGAs; Neuroprocessors; vector quantization; IMPLEMENTATION; RECOGNITION; SOM; PARALLEL; SYSTEM;
D O I
10.1142/S0218126620500024
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we present a new generic architectural approach of a Self-Organizing Map (SOM). The proposed architecture, called the Diagonal-SOM (D-SOM), is described as an Hardware- Description-Language as an intellectual property kernel with easily adjustable parameters.The D-SOM architecture is based on a generic formalism that exploits two levels of the nested parallelism of neurons and connections. This solution is therefore considered as a system based on the cooperation of a distributed set of independent computations. The organization and structure of these calculations process an oriented data flow in order to find a better treatment distribution between different neuroprocessors. To validate the D-SOM architecture, we evaluate the performance of several SOM network architectures after their integration on a Xilinx Virtex-7 Field Programmable Gate Array support. The proposed solution allows the easy adaptation of learning to a large number of SOM topologies without any considerable design effort. 16 x 16 SOM hardware is validated through FPGA implementation, where temporal performance is almost twice as fast as that obtained in the recent literature. The suggested D-SOM architecture is also validated through simulation on variable-sized SOM networks applied to color vector quantization.
引用
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页数:35
相关论文
共 39 条
[1]   A scalable and adaptable hardware NoC-based self organizing map [J].
Abadi, Mehdi ;
Jovanovic, Slavisa ;
Ben Khalifa, Khaled ;
Weber, Serge ;
Bedoui, Mohamed Hedi .
MICROPROCESSORS AND MICROSYSTEMS, 2018, 57 :1-14
[2]   A Modified Parallel Learning Vector Quantization Algorithm for Real-Time Hardware Applications [J].
Alkim, Erdem ;
Akleylek, Sedat ;
Kilic, Erdal .
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2017, 26 (10)
[3]   A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration [J].
An, Fengwei ;
Zhang, Xiangyu ;
Chen, Lei ;
Mattausch, Hans Jurgen .
IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS, 2016, 2 (04) :234-241
[4]   Local adaptive receptive field self-organizing map for image color segmentation [J].
Araujo, Aluizio R. F. ;
Costa, Diogo C. .
IMAGE AND VISION COMPUTING, 2009, 27 (09) :1229-1239
[5]  
Asanovic K, 1997, LECT NOTES COMPUT SC, V1240, P792, DOI 10.1007/BFb0032538
[6]   A Massively Parallel Implementation of a Modular Self-Organizing Map on FPGAs [J].
Ben Khalifa, Khaled ;
Bedoui, Mohamed Hedi .
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2019, 28 (03)
[7]   3D NOSE FEATURE IDENTIFICATION AND LOCALIZATION THROUGH SELF-ORGANIZING MAP AND GRAPH MATCHING [J].
Bevilacqua, Vitoantonio ;
Mastronardi, Giuseppe ;
Santarcangelo, Vito ;
Scaramuzzi, Rocco .
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2010, 19 (01) :191-202
[8]   A survey of optimization techniques for thermal-aware 3D processors [J].
Cao, Kun ;
Zhou, Junlong ;
Wei, Tongquan ;
Chen, Mingsong ;
Hu, Shiyan ;
Li, Keqin .
JOURNAL OF SYSTEMS ARCHITECTURE, 2019, 97 :397-415
[9]  
Chang CH, 2006, FPGA IMPLEMENTATIONS OF NEURAL NETWORKS, P225, DOI 10.1007/0-387-28487-7_8
[10]   A parallel adaptive segmentation method based on SOM and GPU with application to MRI image processing [J].
De, Ailing ;
Zhang, Yuan ;
Guo, Chengan .
NEUROCOMPUTING, 2016, 198 :180-189