A 350 MHz 5.6 GOPS/1.4 GFLOPS 4-way VLIW embedded microprocessor

A 5.6GOPS/1.4GFLOPS 350 MHz, four-way very long instruction word (VLIW) microprocessor is developed for embedded applications in a 0.18 mum five-layer-metal CMOS process. This processor features a two-way integer pipeline and two-way floating/media pipelines. Each floating pipeline and me dia pipeline has two-parallel and four-parallel single instruction multiple-data (SIMD) mechanisms, respectively. The processor has separate instruction and data caches, each of 16KB in size and having four-way set associative. The data cache employs a non-blocking technique and can process two load instructions in parallel. The processor had about a 50% clock net power reduction compared with one without power optimization. 6.7 million transistors are integrated in an area of 7.5 mm x 7.5 mm. Since all circuit blocks were developed using logic synthesis, the pre cesser is easy to adapt to system-on-a-chip (SoC) applications.