Investigation of hot carrier degradation in bulk FinFET

被引：0

作者：

Chung, Eun-Ae ^{[1
]}

Nam, Kab-Jin ^{[1
]}

Nakanishi, Toshiro ^{[1
]}

Park, Sungil ^{[1
]}

Yang, Hongseon ^{[1
]}

Kauerauf, Thomas ^{[1
]}

Jiao, Guangfan ^{[1
]}

Kim, Dong-won ^{[1
]}

Hwang, Ki Hyun ^{[1
]}

Kim, Hyejin ^{[2
]}

Lee, Hyunwoo ^{[2
]}

Pae, Sangwoo ^{[2
]}

机构：

[1] Samsung Elect, Semicond R&D Ctr, 1 Samsungjeonja Ro, Hwasung Si 18448, Gyeonggi Do, South Korea

[2] Samsung Elect, Syst LSI Div, Technol Qual & Reliabil, San 24 Giheung Gu, Yongin 17114, South Korea

来源：

2017 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2017年

关键词：

bulk FinFET; drain avalanche hot carrier; hot carrier injection; impact ionization; interface states;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a physical mechanism for hot carrier injection (HCI) induced trap generation and degradation in bulk FinFETs is investigated and verified with both experiment and simulation evidence. HCI degradation is mainly caused by interface states generated by drain avalanche hot carrier injection. From this model, impact ionization intensity, location and trapping immunity are proposed as key parameters to modulate HCI degradation. HCI reliability in I/O FinFETs is severely degraded with respect to planar FETs because of the enhanced capability of the gate to control the channel potential profiles increasing the intensity of the lateral E-field in comparison with planar devices. Based on this FinFET HCI mechanism, we have successfully optimized source/drain junction process to achieve reliable HCI characteristics for 14nm and 10nm FinFET devices.

引用

页数：4

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