Open-loop full-digital duty cycle correction circuit

被引：16

作者：

Yoo, C

Jeong, C

Kih, J

机构：

[1] Hanyang Univ, Dept Elect & Comp Engn, Seoul 133791, South Korea

[2] Hynix Semicond Inc, DRAM Design, Ichon 467701, Kyong Ki, South Korea

来源：

ELECTRONICS LETTERS | 2005年 / 41卷 / 11期

关键词：

D O I：

10.1049/el:20050776

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The duty cycle of the clock is corrected to be 50% by an open-loop full-digital duty cycle correction (DCC) circuit. Due to its open-loop and full-digital architecture, the DCC completes its operation in less than five clock cycles and can be turned off during power-down state without any concern about losing its information. The DCC has been implemented in a 0.35 mu m CMOS process and the measured accuracy is +/- 0.8% for +/- 10% input clock duty error.

引用

页码：635 / 637

页数：3