In floating gate flash memories, anode hot hole injection induced by the channel FN erase will result in tunnel oxide, degradation, severe read disturbance and an abnormally fast program. All of these issues are critical for multilevel cell (MLC) flash memory design, which requires precise threshold voltage placement, good data retentivity and programming controllability. In this paper, a novel soft-program scheme is proposed to narrow the threshold voltage distribution in the first level. Cycling-induced read disturbance and programming inaccuracy are also reduced. This technique is essential for the application of more-than-2-bit MLC, flash memories.
