An ultra-low-power and portable digitally controlled oscillator for SoC applications

被引:81
作者
Sheng, Duo [1 ]
Chung, Ching-Che [1 ]
Lee, Chen-Yi [1 ]
机构
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
关键词
all-digital phase-locked loop (ADPLL); cell-based design; digitally controlled oscillator (DCO); hysteresis delay cell (HDC); portable; segmental delay line (SDL);
D O I
10.1109/TCSII.2007.903782
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, a novel ultra-low-power digitally controlled oscillator (DCO) with cell-based design for system-on-chip (SoC) applications is presented. Based on the proposed segmental delay line (SDL) and hysteresis delay cell (HDC), the power consumption can be saved by 70% and 86.2% in coarse-tuning and fine-tuning stages, respectively, as compared with conventional approaches. Besides, the proposed DCO employs a cascade-stage structure to achieve high resolution and wide range at the same time. Measurement results show that power consumption of the proposed DCO can be improved to 140 mu W (@200 MHz) with 1.47-ps resolution. In addition, the proposed DCO can be implemented with standard cells, making it easily portable to different processes and very suitable for SoC applications.
引用
收藏
页码:954 / 958
页数:5
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