Technical evaluation of a near chip scale size Flip Chip Plastic Ball Grid Array package

被引：2

作者：

Jimarez, M ^{[1
]}

Li, L ^{[1
]}

Tytran, C ^{[1
]}

Loveland, C ^{[1
]}

Obrzut, J ^{[1
]}

机构：

[1] IBM Microelect, Endicott, NY 13760 USA

来源：

48TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1998 PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/ECTC.1998.678739

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Technical evaluation and reliability assessment have been performed for a near chip scale size package that utilizes microvias and the Flip Chip Plastic Ball Grid Array technology. The microvias were photolithographically patterned in a build-up, Surface Laminar Circuit (TM) (SLC) interposer layers. The package accomodated a 12 mm x 14 mm die with 700 controlled collapse chip connections (C4). The carrier dimensions were 21 mm x 21 mm, 1.27 mm pitch with 255 EGA interconnections. The dimensions of the package, for which the target application was microprocessors, conformed to the JEDEC standards. It has been determined that this novel packaging construction is manufacturable and can satisfy the standard reliability requirements.

引用

页码：495 / 502

页数：8