A Quasi-Two-Dimensional Threshold Voltage Model for Short-Channel Junctionless Double-Gate MOSFETs

被引：126

作者：

Chiang, Te-Kuang ^{[1
]}

机构：

[1] Natl Univ Kaohsiung, Dept Elect Engn, Adv Devices Simulat Lab, Kaohsiung 700, Taiwan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2012年 / 59卷 / 09期

关键词：

Bulk conduction mode; junctionless (JL) doublegate MOSFETs; quasi-2-D scaling theory; threshold voltage; TRANSISTORS; NANOWIRE;

D O I：

10.1109/TED.2012.2202119

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Based on the bulk conduction mode of the quasi-2-D scaling theory, an analytical threshold voltage model for short-channel junctionless (JL) double-gate MOSFETs is developed for the first time. The model explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage degradation. The model can also be extended to modeling accumulation/inversion operation mode for JL/junction-based double-gate MOSFETs. The model is verified by 2-D device simulations and can be easily used to explore the threshold voltage behavior of the JL double-gate MOSFETs due to its simple formula and computational efficiency.

引用

页码：2284 / 2289

页数：6

共 21 条

[1]

[Anonymous], 2003, DESSIS 3 D DEV SIM I

[2] A new scaling theory for fully-depleted SOI double-gate MOSFET's: including effective conducting path effect (ECPE) [J].

Chiang, TK .

SOLID-STATE ELECTRONICS, 2005, 49 (03) :317-322

[3] Nonvolatile Memory by All-Around-Gate Junctionless Transistor Composed of Silicon Nanowire on Bulk Substrate [J].

Choi, Sung-Jin ;

Moon, Dong-Il ;

Kim, Sungho ;

Ahn, Jae-Hyuk ;

Lee, Jin-Seong ;

Kim, Jee-Yeon ;

Choi, Yang-Kyu .

IEEE ELECTRON DEVICE LETTERS, 2011, 32 (05) :602-604

[4]

Colinge JP, 2010, NAT NANOTECHNOL, V5, P225, DOI [10.1038/nnano.2010.15, 10.1038/NNANO.2010.15]

[5] Analytical Model of Subthreshold Current and Slope for Asymmetric 4-T and 3-T Double-Gate MOSFETs [J].

Dey, Aritra ;

Chakravorty, Anjan ;

DasGupta, Nandita ;

DasGupta, Amitava .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (12) :3442-3449

[6] Junctionless Multiple-Gate Transistors for Analog Applications [J].

Doria, Rodrigo Trevisoli ;

Pavanello, Marcelo Antonio ;

Trevisoli, Renan Doria ;

de Souza, Michelly ;

Lee, Chi-Woo ;

Ferain, Isabelle ;

Akhavan, Nima Dehdashti ;

Yan, Ran ;

Razavi, Pedram ;

Yu, Ran ;

Kranti, Abhinav ;

Colinge, Jean-Pierre .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (08) :2511-2519

[7] A Nonpiecewise Model for Long-Channel Junctionless Cylindrical Nanowire FETs [J].

Duarte, Juan P. ;

Choi, Sung-Jin ;

Moon, Dong-Il ;

Choi, Yang-Kyu .

IEEE ELECTRON DEVICE LETTERS, 2012, 33 (02) :155-157

[8] Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors [J].

Duarte, Juan P. ;

Choi, Sung-Jin ;

Moon, Dong-Il ;

Choi, Yang-Kyu .

IEEE ELECTRON DEVICE LETTERS, 2011, 32 (06) :704-706

[9] A Full-Range Drain Current Model for Double-Gate Junctionless Transistors [J].

Duarte, Juan Pablo ;

Choi, Sung-Jin ;

Choi, Yang-Kyu .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (12) :4219-4225

[10] Theory of the Junctionless Nanowire FET [J].

Gnani, Elena ;

Gnudi, Antonio ;

Reggiani, Susanna ;

Baccarani, Giorgio .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (09) :2903-2910

← 1 2 3 →