Integrated Power Delivery Methodology for 3D ICs

Efficient power delivery is a critical enabler for the future of three-dimensional integrated circuits (3D ICs). To this end, on-chip power demand, impedance of power delivery paths (on- and off-chip), and heat dissipation, need to be considered simultaneously. Given the high off-chip porosities, power conversion within the 3D stack (on-chip) is a promising solution to overcome key power delivery challenges in 3D ICs. Recent developments in fabrication of high-density on-chip passive components have paved the way for the implementation of fully integrated voltage regulators (FIVRs). This work builds on the FIVR approach to propose an efficient integrated power delivery methodology for 3D ICs. In the proposed methodology, depending on the number of layers and the power characteristics of each layer, one or more layers of the 3D structure are dedicated to power conversion, regulation, and management. A case study of a five-layer 3D IC is considered where the proposed methodology is compared with conventional and FIVR-based approaches under, both, static and transient conditions. The proposed methodology exhibits a reduction in power loss and voltage drop of, respectively, 5X and 24X, while occupying a significantly smaller horizontal area, as compared to the other approaches.