Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (≤ 50 mV/decade) at Room Temperature

被引：283

作者：

Gandhi, Ramanathan ^{[1
,2
]}

Chen, Zhixian ^{[1
]}

Singh, Navab ^{[1
]}

Banerjee, Kaustav ^{[3
]}

Lee, Sungjoo ^{[2
]}

机构：

[1] ASTAR, Inst Microelect, Singapore 117685, Singapore

[2] Natl Univ Singapore, Dept Elect & Comp Engn, Singapore 117576, Singapore

[3] Univ Calif Santa Barbara, Dept Elect & Comp Engn, Santa Barbara, CA 93106 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 2011年 / 32卷 / 04期

关键词：

CMOS technology; gate-all-around (GAA); subthreshold swing (SS); top-down; tunneling field-effect transistor (TFET); vertical silicon nanowire (NW) (SiNW);

D O I：

10.1109/LED.2011.2106757

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high I(on)/I(of)f ratio (similar to 10(5)), as well as low Drain-Induced Barrier Lowering of similar to 70 mV/V.

引用

页码：437 / 439

页数：3

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