Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (≤ 50 mV/decade) at Room Temperature

被引:283
作者
Gandhi, Ramanathan [1 ,2 ]
Chen, Zhixian [1 ]
Singh, Navab [1 ]
Banerjee, Kaustav [3 ]
Lee, Sungjoo [2 ]
机构
[1] ASTAR, Inst Microelect, Singapore 117685, Singapore
[2] Natl Univ Singapore, Dept Elect & Comp Engn, Singapore 117576, Singapore
[3] Univ Calif Santa Barbara, Dept Elect & Comp Engn, Santa Barbara, CA 93106 USA
关键词
CMOS technology; gate-all-around (GAA); subthreshold swing (SS); top-down; tunneling field-effect transistor (TFET); vertical silicon nanowire (NW) (SiNW);
D O I
10.1109/LED.2011.2106757
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high I(on)/I(of)f ratio (similar to 10(5)), as well as low Drain-Induced Barrier Lowering of similar to 70 mV/V.
引用
收藏
页码:437 / 439
页数:3
相关论文
共 15 条
[1]   Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering [J].
Bhuwalka, KK ;
Schulze, J ;
Eisele, I .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (05) :909-917
[2]   Double-gate tunnel FET with high-κ gate dielectric [J].
Boucart, Kathy ;
Mihai Ionescu, Adrian .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (07) :1725-1733
[3]   Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires [J].
Chen, Z. X. ;
Yu, H. Y. ;
Singh, N. ;
Shen, N. S. ;
Sayanthan, R. D. ;
Lo, G. Q. ;
Kwong, D. -L. .
IEEE ELECTRON DEVICE LETTERS, 2009, 30 (07) :754-756
[4]   Dopant-Segregated Schottky Silicon-Nanowire MOSFETs With Gate-All-Around Channels [J].
Chin, Yoke King ;
Pey, Kin-Leong ;
Singh, Navab ;
Lo, Guo-Qiang ;
Tan, Khing Hong ;
Ong, Chio-Yin ;
Tan, L. H. .
IEEE ELECTRON DEVICE LETTERS, 2009, 30 (08) :843-845
[5]   Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec [J].
Choi, Woo Young ;
Park, Byung-Gook ;
Lee, Jong Duk ;
Liu, Tsu-Jae King .
IEEE ELECTRON DEVICE LETTERS, 2007, 28 (08) :743-745
[6]   Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current [J].
Guo, Peng-Fei ;
Yang, Li-Tao ;
Yang, Yue ;
Fan, Lu ;
Han, Gen-Quan ;
Samudra, Ganesh S. ;
Yeo, Yee-Chia .
IEEE ELECTRON DEVICE LETTERS, 2009, 30 (09) :981-983
[7]   Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits [J].
Khatami, Yasin ;
Banerjee, Kaustav .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2009, 56 (11) :2752-2761
[8]  
Krishnamohan T, 2008, INT EL DEVICES MEET, P947
[9]  
Mayer F, 2008, INT EL DEVICES MEET, P163
[10]   Design of tunneling field-effect transistors using strained-silicon/strained-germanium type-II staggered heterojunctions [J].
Nayfeh, Osama M. ;
Chleirigh, Cait Ni ;
Hennessy, John ;
Gomez, Leonardo ;
Hoyt, Judy L. ;
Antoniadis, Dimitri A. .
IEEE ELECTRON DEVICE LETTERS, 2008, 29 (09) :1074-1077