An Investigation of Phase Noise of a Fractional-N PLL in the Course of FMCW Chirp Generation

被引:4
作者
Ergintav, Arzu [1 ]
Herzel, Frank [1 ]
Kissinger, Dietmar [1 ]
Ng, Herman Jalli [1 ]
机构
[1] IHP, Technol Pk 25, D-15236 Frankfurt, Oder, Germany
来源
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2018年
关键词
Fractional-N PLL; frequency synthesizer; frequency modulated continuous wave (FMCW); radar; ramp generators; phase noise; jitter; FREQUENCY RAMP GENERATOR;
D O I
10.1109/ISCAS.2018.8351072
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, thermal and 1/f noise of a fractional-N charge pump (CP) phase-locked loop (PLL) are described in the framework of a linear, time-invariant continuous-time model. An optimization guideline for minimizing the in-band phase noise of an integrated fractional-N PLL for generating a frequency-modulated continuous-wave (FMCW) signal is presented. Under such an operational condition, the PLL output frequency is not constant but is linearly changing in time. Hence, not the PLL output, but the programmable feedback divider output is monitored to investigate the phase noise dependence on the loop parameters and the ramp slope. For this purpose, the phase noise of this signal is measured as a function of charge pump current, loop filter capacitance and sweep time. The resulting low-frequency rms jitter is reduced by about 9 dB with doubling the charge pump current and reduced by about 6 dB with doubling the sweep time. These findings are in good agreement with the developed phase-noise model for charge pump PLLs under FMCW modulation. A programmable loop filter capacitance is suggested to accommodate the static phase offset to the ramp slope.
引用
收藏
页数:4
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