Experimental characterization of bit error rate and pulse jitter in RSFQ circuits

Rapid Single Flux Quantum (RSFQ) logic is well-known for its ultra-high switching speed and extremely low power consumpition. In this paper, we present two original experiments to demonstrate that it's also a reliable technology and its reliability is sufficient even for such a large-scale system as a proposed petaflops-scale HTMT computer. We have measured the bit error rate (BER) for a circular register of inverters representing a critical path of a 64-bit integer adder, and timing jitter in a 200 Josephson junction (JJ) long transmission line, imitating a branch of a clock distribution tree, both being important and representative building blocks of the HTMT computer. For the adder critical path we have demonstrated the highest clock frequency of 17GHz, latency of 860 Ds and BER of 10(-19) for 3.5 mum technology of HYPRES, Inc. The value of timing jitter was 200 fs per JJ for 1.5 mum technology of TRW, Inc. These figures are in good agreement with our simulations.