Mathematical Modelling of an Application Specific Processor Architecture with Power Optimization

被引：0
作者：
Saravanan, Vijayalakshmi [1 ]
Pillai, Anju S. [2 ]
Naik, Kshirasagar [3 ]
机构：
[1] Univ South Dakota, Dept Comp Sci, Vermillion, SD 57069 USA
[2] AmritaVishwa Vidyapeetham, Amrita Sch Engn, Dept Elect & Elect Engn, Coimbatore, Tamil Nadu, India
[3] Univ Waterloo, Dept Elect & Comp Engn, Waterloo, ON, Canada
来源：
2021 IEEE INTERNATIONAL WOMEN IN ENGINEERING (WIE) CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (WIECON-ECE) | 2022年
关键词：
Mathematical modelling; power-performance optimization; instruction scheduling; pipeline configuration; REGRESSION-MODELS; PERFORMANCE;
D O I：
10.1109/WIECON-ECE54711.2021.9829608
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Analytical and mathematical modelling has gained an increased interest as the power concerns are continually increasing in the computing systems. Optimizing power and performance for application specific processors can substantially increase the energy-efficiency. However, designing an application specific processor architecture requires an exploration of microarchitectural parameters. Mathematical models are suitable for providing insights into the specific application and its impacts on the micro-architecture. Unfortunately, current architectural models lack some microarchitectural inputs. The paper presents a mathematical model and associates the micro-architectural needs to estimate the power and performance for an application specific architecture. This paper deals with the instruction scheduling in a processor architecture with latency to optimize the power and performance. The proposed model includes the latency depending on the tasks/applications and functional units.
引用
收藏
页码：55 / 58
页数：4
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