Effects of DC gate and drain bias stresses on the degradation of excimer laser crystallized polysilicon thin film transistors

The effects of gate and drain bias stresses on thin film transistors fabricated in polysilicon films crystallized using the advanced sequential lateral solidification excimer laser annealing (SLS ELA) process, which yields very elongated polysilicon grains and allows the fabrication of TFTs without grain boundary barriers to current flow, are investigated as a function of the active layer thickness and of the TFT orientation relative to the grains. The application of hot carrier stress, with a condition of V-GS = V-DS/2, was determined to induce threshold voltage, subthreshold swing and transconductance degradation for TFTs in thicker polysilicon films and the associated stress-induced increase in the active layer trap density was evaluated. However, this device degradation was drastically reduced for TFTs fabricated in ultra-thin films. Furthermore, the application of the same stress condition to TFTs oriented vertically to the elongated grains resulted in similar threshold voltage shift but in substantially decreased subthreshold swing and transconductance degradation. The immunity of ultra-thin active layer devices to degradation under hot carrier stress clearly suggests the implementation of ultra thin SLS ELA polysilicon films for the fabrication of TFTs exhibiting not only high performance but, especially, the high reliability needed for integrated systems on panel.