Measurement and characterization of multilayered interconnect capacitance for deep-submicron VLSI technology

This paper presents the measurement and characterization of multilayered interconnect capacitances for a 0.35-mu m CMOS logic technology, which become a critical circuit limitation to high performance VLSI design. To measure multilayered capacitances of nonstacked, stacked, and orthogonally crossing interconnect lines, new test structures and measurement method are presented. The measured interconnect capacitances were employed to evaluate and calibrate TCAD tools for the simulation of high-speed interconnect technologies. This study shows that the calibration method considerably improves the accuracy of simulation results compared with measured results.