The Speed-Power Trade-Off in the Design of CMOS True-Single-Phase-Clock Dividers

被引：42
作者：
Deng, Zhiming [1 ]
Niknejad, Ali M. [2 ]
机构：
[1] MediaTek USA Inc, San Jose, CA 95134 USA
[2] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2010年 / 45卷 / 11期
关键词：
Frequency divider; high-speed; prescaler; low-power; true-single-phase-clock (TSPC); OPTIMIZATION;
D O I：
10.1109/JSSC.2010.2074290
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this work, we introduce a true-single-phase-clock (TSPC) divider synthesis technique that is based on the general TSPC logic family. According to this unified technique, various types of TSPC dividers are compared in terms of the speed-power trade-off. The newly proposed RE-2 type has shown better balance between speed and power performance than other types. The measurement results of a prototype design in a 65 nm LP CMOS technology show that the maximal input frequencies can be 19 GHz and 16 GHz for a divide-by-2 divider and a divide-by-2/3 prescaler respectively, and the power consumption is less than 0.5 mW.
引用
收藏
页码：2457 / 2465
页数：9
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