Hole Mobility Characteristics in Si Nanowire pMOSFETs on (110) Silicon-on-Insulator

被引：13
作者：
Chen, Jiezhi [1 ]
Saraya, Takuya [2 ]
Hiramoto, Toshiro [2 ]
机构：
[1] Univ Tokyo, Inst Ind Sci, Tokyo 1538505, Japan
[2] Univ Tokyo, Inst Ind Sci, Tokyo 1538505, Japan
来源：
IEEE ELECTRON DEVICE LETTERS | 2010年 / 31卷 / 11期
关键词：
Gate-all-around (GAA) nanowire; hole mobility; Si; split C-V method; (110) silicon-on-insulator (SOI); STRAIN;
D O I：
10.1109/LED.2010.2064154
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this letter, hole mobility characteristics in Si gate-all-around nanowires on (110)-oriented silicon-on-insulator substrate have been studied, based on the advanced split C-V method. Fabricated nanowires have rectangular shape, and the height is fixed to 18 nm. High hole mobility in [110]-directed nanowires (widths ranging from 25 to 68 nm) were observed, illustrating 2.4x enhancements over the universal (100) hole mobility in high N-inv region. Furthermore, effects of uniaxial stress in nanowires were investigated. It was found that [110]-directed nanowires were more sensitive to the applied stress in high N-inv region. Underlying physical mechanisms are also discussed.
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收藏
页码：1181 / 1183
页数：3
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