A 200MSPS Time-Interleaved 12-bit ADC System with Digital Calibration

被引：0

作者：

Bommireddipalli, Aditya ^{[1
]}

Zhou, Dadian ^{[1
]}

Talarico, Claudio ^{[2
]}

Silva-Martinez, Jose ^{[1
]}

Karsilayan, Aydin I. ^{[1
]}

机构：

[1] Texas A&M Univ, Elect & Comp Engn Dept, College Stn, TX 77843 USA

[2] Gonzaga Univ, Elect Engn Dept, Spokane, WA 99258 USA

来源：

2017 IEEE 60TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2017年

关键词：

CONVERTER;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a time interleaved ADC architecture employing a digital background calibration technique based on evolutionary-computation. The algorithm iteratively minimizes an error function (EF) which models the gain, offset and timing mismatches between the ADC channels. The system was implemented using off-the-shelf Analog to Digital Converters (ADCs) and a Field Programmable Gate Array (FPGA). Experimental results demonstrate that the proposed calibration technique allows an SNDR improvement of 26dB for just 32 iterations of calibration.

引用

页码：1184 / 1187

页数：4

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