Memory controller policies for DRAM power management

被引：59

作者：

Fan, XB ^{[1
]}

Ellis, CS ^{[1
]}

Lebeck, AR ^{[1
]}

机构：

[1] Duke Univ, Dept Comp Sci, Durham, NC 27708 USA

来源：

ISLPED'01: PROCEEDINGS OF THE 2001 INTERNATIONAL SYMPOSIUM ON LOWPOWER ELECTRONICS AND DESIGN | 2001年

关键词：

D O I：

10.1109/LPE.2001.945388

中图分类号：

TE [石油、天然气工业]; TK [能源与动力工程];

学科分类号：

0807 ; 0820 ;

摘要：

The increasing importance of energy efficiency has produced a multitude of hardware devices with various power management features. This paper investigates memory controller policies for manipulating DRAM power states in cache-based systems. We develop an analytic model that approximates the idle time of DRAM chips using an exponential distribution, and validate our model against trace-driven simulations. Our results show that, for our benchmarks, the simple policy of immediately transitioning a DRAM chip to a lower power state when it becomes idle is superior to more sophisticated policies that try to predict DRAM chip idle time.

引用

页码：129 / 134

页数：6