Using pattern analysis methodology to do fast detection of manufacturing pattern failure.

被引：1

作者：

Zhao, Evan ^{[1
]}

Wang, Jessie ^{[1
]}

Sun, Mason ^{[1
]}

Wang, Jeff ^{[1
]}

Zhang, Yifan ^{[2
]}

Sweis, Jason ^{[2
]}

Lai, Ya-Chieh ^{[2
]}

Ding, Hua ^{[2
]}

机构：

[1] Semicond Mfg Int Corp, Pudong New Area, 18 Zhangjiang Rd, Shanghai 201203, Peoples R China

[2] Cadence Design Syst Inc, 2655 Seely Ave, San Jose, CA 95134 USA

来源：

DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY X | 2016年 / 9781卷

关键词：

Pattern; DFT; systematic design failure; electrical failure analysis; yield;

D O I：

10.1117/12.2219000

中图分类号：

O43 [光学];

学科分类号：

070207 ; 0803 ;

摘要：

At the advanced technology node, logic design has become extremely complex and is getting more challenging as the pattern geometry size decreases. The small sizes of layout patterns are becoming very sensitive to process variations. Meanwhile, the high pressure of yield ramp is always there due to time-to-market competition. The company that achieves patterning maturity earlier than others will have a great advantage and a better chance to realize maximum profit margins. For debugging silicon failures, DFT diagnostics can identify which nets or cells caused the yield loss. But normally, a long time period is needed with many resources to identify which failures are due to one common layout pattern or structure. This paper will present a new yield diagnostic flow, based on preliminary EFA results, to show how pattern analysis can more efficiently detect pattern related systematic defects. Increased visibility on design pattern related failures also allows more precise yield loss estimation.

引用

页数：7