A Fast and Low-power VLSI Architecture for Half-pixel Motion Estimation Using Two-step Search Algorithm for HDTV Application

被引：1

作者：

Chatterjee, Sumit K. ^{[1
]}

Chakrabarti, Indrajit ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect & Elect Commun Engn, Kharagpur 721302, W Bengal, India

来源：

IETE JOURNAL OF RESEARCH | 2011年 / 57卷 / 03期

关键词：

Half-pixel motion estimation; High Definition Tele-vision (HDTV); Interpolation; Memory bandwidth; VLSI architecture;

D O I：

10.4103/0377-2063.83648

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The present article proposes a high-performance architecture for the Two-Step Search algorithm, which is used in half-pixel motion estimation. As motion estimation calls for intense computation on a large number of pixels stored in memory, frequent memory access is involved in this operation. In the present article, an architecture, which is based on an intelligent memory configuration to contain the required large memory bandwidth, has been proposed for implementing the Two-Step Search algorithm for variable block sizes as recommended by H.264 standard. The present architecture has been compared with a reported architecture. It has been found that the proposed architecture can process up to 33% more number of High Definition Tele-Vision frames (of size 1280x720) and also consumes 5% less power by sacrificing only about 1.6% of the total chip area.

引用

页码：263 / 270

页数：8