A 2.5 GHz radiation hard fully self-biased PLL using 0.25 μm SOS-CMOS technology

This paper presents a radiation hard phase locked loop (PLL) using 0.25 gm SOS-CMOS technology for radiation environments. Radiation effects on transistors and circuits are evaluated experimentally. The degraded parameters are extracted, and help design the robust PLL. The PLL is fully self-biased and gives output frequency of 2.5GHz. It successfully operates for all the process corners from -40 degrees C to 80 degrees C. A new modification has been done on the differential buffers of the VCO in the PLL to reduce phase noise. Simulation results from extracted layout including buffers and pads are enlisted for pre and post radiation environments.