A 3mW 12b 10MS/s Sub-Range SAR ADC

被引：16

作者：

Chen, Hung-Wei ^{[1
]}

Liu, Yu-Hsun ^{[1
]}

Lin, Yu-Hsiang ^{[1
]}

Chen, Hsin-Shu ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Dept Elect Engn, Taipei 10617, Taiwan

来源：

2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) | 2009年

关键词：

SAR ADC; sub-range; power efficiency;

D O I：

10.1109/ASSCC.2009.5357201

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a successive approximation analog-to-digital converter (SAR ADC) achieving high power efficiency by adopting sub-range concept. Overlapping range greatly relieves the accuracy requirement on the first 6 bit resolving in coarse conversion. The error made in the coarse conversion is recovered during the rest 7 bit resolving in fine conversion. Hence, it significantly reduces the capacitor array output settling time of most-significant-bit (MSB) capacitor switching, which is the speed bottleneck for traditional SAR ADC. A 3mW 12b 10MS/s sub-range SAR ADC is realized in 0.13-mu m CMOS process. The prototype circuit reaches SNDR 59.7dB at Nyquist input frequency. It occupies an active chip area of 0.096 mm(2).

引用

页码：153 / 156

页数：4

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