Development of a Low-Noise Front-End Readout Chip Integrated With a High-Resolution TDC for APD-Based Small-Animal PET

被引:12
作者
Fang, X. C. [1 ]
Gao, W. [2 ]
Hu-Guo, Ch. [1 ]
Brasse, D. [1 ]
Humbert, B. [1 ]
Hu, Y. [1 ]
机构
[1] CNRS IN2P3, UDS, Inst Pluridisciplinaire Hubert CURIEN, F-67037 Strasbourg, France
[2] Northwestern Polytech Univ, Xian 710072, Peoples R China
关键词
Charge sensitive amplifier (CSA); delay locked loop (DLL); positron emission tomography (PET); time-to-digital converter (TDC);
D O I
10.1109/TNS.2011.2113191
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents the design of a low-noise multi-channel front-end readout chip integrated with a high-resolution TDC. It is foreseen to be used as front-end readout electronics of Avalanche Photo Diodes (APD) dedicated to a small animal Positron Emission Tomography (PET) system. The architecture of the chip is reported. Two prototype chips, a ten-channel front-end chip and a three-channel high-resolution TDC, have been designed in AMS 0.35 mu m CMOS technology. A low-noise charge-sensitive amplifier (CSA) and a shaper are integrated in each channel of the front-end chip. The proposed CSA performs a compensation of the 40 nA dark current coming from the detector. An equivalent input noise charge of 275 e(-) + 10 e(-)/pF (rms) has been obtained from test. The TDC chip is based on coarse-fine two-level conversion scheme. In the coarse conversion, a 10-bit counter is employed to achieve a wide range. Meanwhile, the time interpolation using an array of delay-locked loops is proposed for fine conversion. The measured time range is 10 mu s. The bin size has been achieved from 71 ps to 142 ps with a reference clock from 100 MHz to 50 MHz.
引用
收藏
页码:370 / 377
页数:8
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