A 15-bit Incremental Sigma-Delta ADC for CMOS Image Sensor

An incremental sigma-delta ADC is designed for column-parallel ADC array in CMOS image sensor. Sigma-delta modulator with single-loop single-bit structure is chosen for power consumption and performance reasons. Second-order modulator is used to reduce conversion time, without stability problem and large area accompanied by higher order sigma-delta modulator. The asymmetric current mirror amplifier used in integrator reduces more than 30% power dissipation. The digital filter and decimator are implemented by counters and adders with significantly reduced chip area and power consumption. A Clock generator is shared by 8 ADCs for trade-off among power, area and clock loading. The ADC array is implemented in a 0.18-mu m CMOS technology and clocked at 10 MHz, and the simulated resolution achieves 15-bit with 255 clock cycles. The average power consumption per ADC is 118 mu W including clock generator, and the area is only 0.0053 mu m(2).