Ternary Logic Flip-Flops Using Quantum Dot Gate Field Effect Transistor (QDGFET)

被引:1
作者
Karmakar, Supriya [1 ]
机构
[1] Farmingdale State Coll SUNY, Dept Elect & Comp Engn Technol, Farmingdale, NY 11735 USA
关键词
Quantum dot; SR latch; metal oxide semiconductor field effect transistor; Very large-scale integration; Nano dots; CIRCUITS; DESIGN;
D O I
10.1007/s12633-022-01949-4
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
In this paper, ternary logic SR, JK and D Flip-Flops using three-state quantum dot gate field effect transistors are introduced. Due to the change in the threshold voltage, Quantum dot gate field effect transistors (QDGFETs) produce an intermediate state between the on and the off state of the device. The author has developed a simplified circuit model that accounts for this intermediate state. Interesting logic can be implemented using quantum dot gate field effect transistors. In this work, designs of different Flip-Flops in ternary logic using QDGFET based ternary NAND and ternary NOR have been discussed. More states in the QDGFET increase the bit handling capabilities of this device and help us to design complex circuits with fewer circuit elements.
引用
收藏
页码:12553 / 12565
页数:13
相关论文
共 23 条
[11]   Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs [J].
Karmakar, Supriya ;
Chandy, John A. ;
Jain, Faquir C. .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, 21 (05) :793-806
[12]   Fabrication and Circuit Modeling of NMOS Inverter Based on Quantum Dot Gate Field-Effect Transistors [J].
Karmakar, Supriya ;
Chandy, John A. ;
Gogna, Mukesh ;
Jain, Faquir C. .
JOURNAL OF ELECTRONIC MATERIALS, 2012, 41 (08) :2184-2192
[13]  
Kleene SC., 1938, J SYMBOLIC LOGIC, V3, P150, DOI [10.2307/2267778, DOI 10.2307/2267778]
[14]   Resonant tunnelling into the two-dimensional subbands of InSe layers [J].
Kudrynskyi, Zakhar R. ;
Kerfoot, James ;
Mazumder, Debarati ;
Greenaway, Mark T. ;
Vdovin, Evgeni E. ;
Makarovsky, Oleg ;
Kovalyuk, Zakhar D. ;
Eaves, Laurence ;
Beton, Peter H. ;
Patane, Amalia .
COMMUNICATIONS PHYSICS, 2020, 3 (01)
[15]  
Mirzaee RF, 2017, J LOW POWER ELECTRON, V13, P36, DOI 10.1166/jolpe.2017.1463
[16]   A 45nm logic technology with high-k plus metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging [J].
Mistry, K. ;
Allen, C. ;
Auth, C. ;
Beattie, B. ;
Bergstrom, D. ;
Bost, M. ;
Brazier, M. ;
Buehler, M. ;
Cappellani, A. ;
Chau, R. ;
Choi, C. -H. ;
Ding, G. ;
Fischer, K. ;
Ghani, T. ;
Grover, R. ;
Han, W. ;
Hanken, D. ;
Hatttendorf, M. ;
He, J. ;
Hicks, J. ;
Huessner, R. ;
Ingerly, D. ;
Jain, P. ;
James, R. ;
Jong, L. ;
Joshi, S. ;
Kenyon, C. ;
Kuhn, K. ;
Lee, K. ;
Liu, H. ;
Maiz, J. ;
McIntyre, B. ;
Moon, P. ;
Neirynck, J. ;
Pei, S. ;
Parker, C. ;
Parsons, D. ;
Prasad, C. ;
Pipes, L. ;
Prince, M. ;
Ranade, P. ;
Reynolds, T. ;
Sandford, J. ;
Schifren, L. ;
Sebastian, J. ;
Seiple, J. ;
Simon, D. ;
Sivakumar, S. ;
Smith, P. ;
Thomas, C. .
2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, :247-+
[17]   An efficient ternary serial adder based on carbon nanotube FETs [J].
Moaiyeri, Mohammad Hossein ;
Nasiri, Molood ;
Khastoo, Nooshin .
ENGINEERING SCIENCE AND TECHNOLOGY-AN INTERNATIONAL JOURNAL-JESTECH, 2016, 19 (01) :271-278
[18]  
Moore GE, 2003, ISSCC DIG TECH PAP I, V46, P20
[20]   Maintaining the benefits of CMOS scaling when scaling bogs down [J].
Nowak, EJ .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2002, 46 (2-3) :169-180