Implementation of memory tester consisting of SRAM-based reconfigurable cells

被引：0

作者：

Yamagata, Y ^{[1
]}

Ichino, K ^{[1
]}

Arai, M ^{[1
]}

Fukumoto, S ^{[1
]}

Iwasaki, K ^{[1
]}

Sato, M ^{[1
]}

Itabashi, H ^{[1
]}

Murai, T ^{[1
]}

Otsuka, N ^{[1
]}

机构：

[1] Tokyo Metropolitan Univ, Grad Sch Engn, Tokyo 1920397, Japan

来源：

ATS 2003: 12TH ASIAN TEST SYMPOSIUM, PROCEEDINGS | 2003年

关键词：

SRAM test; SRAM-based reconfigurable cell; memory tester marching test;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A scheme for testing SRAMS is proposed with a tester circuit consisting of SRAM-based reconfigurable cells. We first show an approach to reduce the number of reconfigurable cells required for the tester circuit. We then propose a tester for a 4-Mbit SRAM with reconfigurable cells of 16-bit data SRAMs. We also report the implementation of the proposed circuit. Four 16-bit reconfigurable cells, each of which consists of an SRAM and two CPLDs, were implemented, and mounted on a board. We confirmed that the tester functions correctly by performing a marching test.

引用

页码：28 / 31

页数：4

共 6 条

[1]

[Anonymous], 18 IEEE VLSI TEST S

[2]

Semiconductor Industry Association, 2001, INT TECHN ROADM SEM

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IEEE DESIGN & TEST OF COMPUTERS, 1993, 10 (01) :8-14

[4]

VANDEGOOR AJ, 1991, TESTING SEMICONDUTOR

[5]

YAMADA R, 2001, 2001 WORKSH RTL ATPG, P38

[6] Self test architecture for testing complex memory structures [J].

Zarrineh, K ;

Adams, RD ;

Eckenrode, TJ ;

Gregor, SP .

INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS, 2000, :547-556

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