Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency

Crossbar-based neuromorphic chips promise improved energy efficiency for spiking neural networks (SNNs), but suffer from the limited fan-in/fan-out constraints and resource mapping inefficiency. In this paper, we propose a new hardware mechanism to enable configurable combination of cores, called core set. Using this hierarchical method, our end-to-end CSM (which stands for the 'CoreSet Method') framework efficiently solves the fan-in/fan-out issues and significantly improves the resource efficiency. Experiment results show that CSM can efficiently support complex network structures as well as significantly improving accuracies. Up to 4.6% improvement compared with those achieved by other neuromorphic chips (i.e. IBM TrueNorth and Intel Loihi), on the CIFAR-10, CIFAR-100 and SVHN datasets is achieved, matching the accuracies of state-of-the-art SNN models. In addition, compared with IBM TrueNorth, CSM achieves improvements of up to 18.5x, 6.04x and 3.33x in memory efficiency, core efficiency and extrapolated throughput, respectively, thus enabling support for large-scale modern networks (such as VGG). In fact, our method can find optimal core sizes for minimal silicon area. As a proof of concept, we have implemented an FPGA emulation of coreset-supported neuromorphic computing. It achieves up to 7, 737x speed-up compared to software simulation, thus not only facilitating SNN structure exploration and verification in a timely manner, but also enabling earlier prototyping for better neuromorphic hardware performance investigation. (c) 2021 Elsevier B.V. All rights reserved.