Modeling and hardware implementation aspects of fading channel simulators

A channel simulator is an essential component in the development and accurate performance evaluation of wireless systems. Two major approaches have been widely used to produce statistically accurate fading variates, namely shaping the flat spectrum of Gaussian variates using digital filters and sum-of-sinusoids (SOS)-based methods. Efficient design and implementation techniques for these schemes are of particular importance in the design and verification of wireless systems with a relatively large number of channels, such as ad hoc networks. This paper considers the modeling and implementation aspects of fading channel simulators. First, we present a novel computationally efficient implementation of a filter-based fading channel simulator on a single field-programmable gate array (FPGA) device. The new technique significantly alleviates the challenges of real-world testing of communication systems by introducing a fast and area-efficient FPGA implementation of the fading channel. Our fixed-point implementation of a Rayleigh-fading channel simulator on an FPGA utilizes only 3% of the configurable slices, 10% of the dedicated multipliers, and 1% of the available memories on a Xilinx Virtex-II Pro XC2VP100-6 FPGA, while the simulator operates 12.5 times faster than the example sample rate. Then, we describe a compact implementation of the SOS-based fading simulator that uses only 1% of the configurable slices and 1% of the available memories on the same FPGA device while generating over 200 million complex Rayleigh-fading variates per second.