Parallel simulation of ATM switches

A simulation based approach to the problem of performance evaluation of large switching fabrics is presented. Experimental results in the form of cell queuing and buffer occupancy distributions for switches with up to 2048 inputs and outputs operating under a wide variety of loads are presented. The traditional dilemma between simulation model validity and its run-time where a more general purpose model inevitably results in longer run-times, is eliminated by the introduction of a new parameter: the architecture of the simulation platform. With model validity as an invariant, the simulation platform can range from a sequential computer via shared memory and distributed memory general purpose parallel processors up to a dedicated emulator. An analytical model of the class of applications under study gives insight in the influence of machine and problem parameters on simulator run-time performance. Examples of its use for the choice of an optimal parallel architecture for a given problem and of its use for the estimation of application behavior on a given parallel machine architecture are presented.