Time delay handling in dominant pole placement with PID controllers to obtain stability regions using random sampling

被引:15
作者
Halder, Kaushik [1 ]
Das, Saptarshi [2 ,3 ]
Gupta, Amitava [4 ]
机构
[1] Univ Surrey, Dept Mech Engn Sci, Guildford, Surrey, England
[2] Univ Exeter, Coll Engn Math & Phys Sci, Dept Math, Penryn Campus, Penryn TR10 9FE, Cornwall, England
[3] Univ Exeter, Inst Data Sci & Artificial Intelligence, Laver Bldg,North Pk Rd, Exeter EX4 4QE, Devon, England
[4] Jadavpur Univ, Dept Power Engn, Kolkata, India
关键词
Dominant pole placement; PID controller; SOPTD plant; pole-zero matching; Tustin discretization; SYSTEMS; DESIGN;
D O I
10.1080/00207179.2020.1764110
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
This paper proposes a new formulation of proportional-integral-derivative (PID) controller design using the dominant pole placement method for handling second-order-plus-time-delay (SOPTD) systems. It transforms the transcendental exponential delay term of the plant into finite number of discrete-time poles by a suitable choice of the sampling time. The PID controller has been discretised using Tustin's method and the controller gains are obtained using the dominant pole placement criterion where the plant is discretized using the pole-zero matching method. Random search and optimisation have been used to obtain the stability region in the desired closed loop parameters space by minimising the integral squared error (ISE) criterion by randomly sampling from the stabilizable region. Then these closed loop parameters are mapped on to the PID controller gains. Effectiveness of the proposed methodology is shown for nine test-bench plants with different lag to delay ratios, open loop damping, and sampling times.
引用
收藏
页码:3384 / 3405
页数:22
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