Training-Based Forming Process for RRAM Yield Improvement

被引:0
作者
Shih, Hsiu-Chuan [1 ]
Chen, Ching-Yi [1 ]
Wu, Cheng-Wen [1 ]
Lin, Chih-He [2 ]
Sheu, Shyh-Shyuan [2 ]
机构
[1] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu, Taiwan
[2] Ind Technol Res Inst, Elect & Optoelect Res Lab, Hsinchu, Taiwan
来源
2011 IEEE 29TH VLSI TEST SYMPOSIUM (VTS) | 2011年
关键词
RRAM; forming process; training sequence; yield improvement; non-volatile memory; memory testing;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Over the past decade, the resistive memory device known as RRAM has been studied extensively in many ways, and many of its problems have been identified, discussed, and some solved. It is time to move from material, process, and device to circuit design and yield, in order to commercialize RRAM. However, as we move from resistive device to memory circuit, new problems do appear, partly because the operating conditions of resistive devices on real RRAM circuit differ from those in an experimental environment for single devices. In this paper, an over forming problem has been identified from our analysis, and we propose a solution based on training sequence. As a result, by solving the over forming problem, RRAM yield can be improved significantly.
引用
收藏
页码:146 / 151
页数:6
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