Research on Crosstalk Issue of Through Silicon Via for 3D Integration

被引:0
|
作者
Kang, Ting [1 ]
Yan, Zhaowen [1 ]
Zhang, Wei [1 ]
Wang, Jianwei [1 ]
机构
[1] Beihang Univ, Sch Elect & Informat Engn, Beijing 100191, Peoples R China
来源
2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC) | 2015年
关键词
Electrical modeling of TSV; NEXT and FEXT crosstalk; Crosstalk suppression; 3D integration;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper focused on the crosstalk analysis of through silicon via (TSV) for 3D integration. It started with the TSV electrical character. A GS TSV pair was established in HFSS and its electrical model was created in ADS. The S-parameter showed a good match between the two methods which validated the electrical model. Crosstalk analysis was an important part in this paper. First, the S-parameter of GSSG-BUMP-RDL model was simulated from 0.1GHz to 20GHz in HFSS, and the NEXT and FEXT crosstalk at 1GHz and 10GHz were given respectively in time domain. Then we added more ground TSV to the model to suppress the crosstalk. And it showed a better capacity to suppress the FEXT crosstalk. Finally, another improved model which used a ground plane to replace the ground RDL was carried out, and it resulted in a better performance to decrease the NEXT crosstalk.
引用
收藏
页码:396 / 400
页数:5
相关论文
共 50 条
  • [1] Feasibility of coaxial through silicon via 3D integration
    Adamshick, S.
    Coolbaugh, D.
    Liehr, M.
    ELECTRONICS LETTERS, 2013, 49 (16) : 1028 - 1029
  • [2] Copper Through Silicon Via (TSV) for 3D integration
    Kothandaraman, C.
    Himmel, B.
    Safran, J.
    Golz, J.
    Maier, G.
    Farooq, M. G.
    Graves-Abe, T.
    Landers, W.
    Volant, R.
    Petrarca, K.
    Chen, F.
    Sullivan, T. D.
    LaRosa, G.
    Robson, N.
    Hannon, R.
    Iyer, S. S.
    2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2012,
  • [3] Through silicon via copper electrodeposition for 3D integration
    Beica, Rozalia
    Sharbono, Charles
    Ritzdorf, Tom
    58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, : 577 - +
  • [4] Considerations on Integration of Through Silicon Via with 3D NAND Scaling
    Lu, Mei-Chien
    2019 IEEE 21ST ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2019, : 6 - 12
  • [5] Investigation of different methods for isolation in through silicon via for 3D integration
    Sage, Stephane
    John, Peggy
    Dobritz, Stephan
    Boernge, Jochen
    Vitiello, Julien
    Boettcher, Matthias
    MICROELECTRONIC ENGINEERING, 2013, 107 : 61 - 64
  • [6] Thermal Management of 3D IC Integration with TSV (Through Silicon Via)
    Lau, John H.
    Yue, Tang Gong
    2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4, 2009, : 635 - +
  • [7] Role of Through Silicon Via in 3D Integration: Impact on Delay and Power
    Chandrakar, Shivangi
    Gupta, Deepika
    Majumder, Manoj Kumar
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2021, 30 (03)
  • [8] Novel Through-Silicon Via Technologies for 3D System Integration
    Thadesar, Paragkumar A.
    Dembla, Ashish
    Brown, Devin
    Bakir, Muhannad S.
    PROCEEDINGS OF THE 2013 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC), 2013,
  • [9] Fabrication and Feasibility of Through Silicon Via for 3D MEMS Resonator Integration
    Soydan, Alper Kaan
    Yuksel, Muhammed Berat
    Akcakaya, Dilek Isik
    Kulah, Haluk
    2019 IEEE SENSORS, 2019,
  • [10] Modeling and Electromagnetic Analysis of Multilayer Through Silicon Via Interconnect for 3D Integration
    Yan, Zhaowen
    Kang, Ting
    Zhang, Wei
    Wang, Jianwei
    INTERNATIONAL JOURNAL OF ANTENNAS AND PROPAGATION, 2015, 2015