Graphical design techniques for fixed-point multiplication

This is a tutorial paper that examines the problem of performing fixed-point constant integer multiplications using as few adders as possible. The driving application is the design of digital filters, where it is often required that several products of a single multiplicand are produced. Thus two specific problems are examined in detail, i.e., the one-input/one-output case and the one-input/several-output case. The latter is of interest because it can take advantage of redundancy in the different coefficient multipliers. Graphical methods can be used to design multipliers in both cases. For the one-input/one-output case, both optimal and sub-optimal algorithms introduced by the author are shown to be the best methods for the design of these multipliers. The key to the new methods' success is the: use of different graph topologies to those available under standard methods. The optimal method uses an exhaustive search and is limited to short wordlengths, so the suboptimal methods must be used for long wordlengths. The design is shown to be analogous to the design of algorithms for exponentiation, which is becoming increasingly important in cryptography. For the one-input/several-output ("multiplier block") case, again new algorithms designed by the author are shown to be the best. When used for designing digital filters, the multiplier block method is more efficient (uses fewer adders) than any other method that has been examined. It is so successful at reducing the number of adders used for multiplication that the non-multiplier elements begin to dominate the overall filter cost. It also allows previously unpopular filter structures to compete with structures like the lattice wave structure, despite having more coefficients of longer wordlength. The use of multiplier blocks in filter banks is also described. A third case is examined briefly, that of matrix multiplication (several-input/several-output), which is an area of further research.