Functional verification of the IBM System z10 processor chipset

被引：9

作者：

Krygowski, C. A. ^{[1
]}

Bair, D. G. ^{[1
]}

Gott, R. M. ^{[1
]}

Decker, M. H. ^{[1
]}

Giri, A. V. ^{[2
]}

Habermann, C. ^{[3
]}

Heizmann, M. ^{[1
]}

Letz, S. ^{[3
]}

Lewis, W. J. ^{[1
]}

Licker, S. M. ^{[1
]}

Mallar, H. ^{[1
]}

McCain, E. C. ^{[1
]}

Roesner, W. ^{[2
]}

Siddique, N. ^{[1
]}

Seigler, A. E. ^{[1
]}

Thompto, B. W. ^{[2
]}

Weber, K. ^{[3
]}

Winkelmann, R. ^{[3
]}

机构：

[1] IBM Syst & Technol Grp, Poughkeepsie, NY 12601 USA

[2] IBM Syst & Technol Grp, Austin, TX 78758 USA

[3] IBM Syst & Technol Grp, D-71032 Boblingen, Germany

来源：

IBM JOURNAL OF RESEARCH AND DEVELOPMENT | 2009年 / 53卷 / 01期

关键词：

MICROPROCESSOR; ARCHITECTURE; DESIGN;

D O I：

10.1147/JRD.2009.5388578

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes the comprehensive verification effort of the IBM System z10 (TM) processor chipset, which consists of the z10 (TM) quad-core central processor chip and the companion z10 symmetric multiprocessor (SMP) chip. The z10 processor chipset represented a significant redesign of its predecessor and thus presented a new challenge to ensure complete functional correctness of the product before the construction of actual system hardware. The z10 microprocessor pipeline was completely redesigned to support a doubling of the operating frequency. It also includes new hardware performance features, such as enhanced branch prediction, a reoptimized cache hierarchy, hardware-based prefetching, and a hardware implementation of decimal floating-point arithmetic in IEEE formats. In addition, there were significant hardware changes in the SMP storage hierarchy for optimized data latency performance. These changes include a new system topology, interprocessor book protocol, larger SMP size, and various aggressive cache ownership schemes. Key verification innovations are described, and a direct relationship to improved z10 system quality is provided for most cases.

引用

页数：11

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